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Description
The GX5290 Series are a high performance, cost-effective 3U PXI dynamic digital I/O boards offering 32 digital input or output channels with dynamic direction control. The GX5290 Series also supports deep pattern memory by offering 256 MB of on-board vector memory with dynamic per pin direction control and with test rates up to 200 MHz. The single board design supports both master and slave functionality without the use of add-on modules.
Features
The GX5290 Series supports selecable I/O levels of 1.5 V, 1.8 V, 2.5 V, or 3.3 V (TTL, LVTTL, CMOS, LVCMOS). In addition, the GX5290 Series support 32 differential channels for LVDS, M-LVDS, or LVDM logic families. The TTL / LVTTL interface utilizes a programmable voltage source, which sets the output logic levels fro 1.4 V to 3.6 V. Programmable thresholds of 1.5 V, 1.8 V, 2.5 V or 3.3 V (5 V compatible) are supported for input signals. Recommended operating input voltage range is from 0 V to 5.5 V.
A windowing method is utilized for PCI memory accesses, which limits the required PCI memory space for each board to only 16 MB, thus preserving test system resources. A direct mode, for continuous data transfer between the test system controller and the I/O pins of the GX5290 Series are also supported.
The GX5290 Series offers 256 MB of vector memory, with 64 Mb per channel. Programmable I/O width allows trading vector width for vector depth. Under software control, the GX5290 Series's vector memory can be configured to support channel widths of 32, 16, 8, 4, 2 and 1 with corresponding vector depths of 64 Mb, 128 Mb, 256 Mb, 512 Mb, 1024 Mb, and 2048 Mb.
The GX5290 Series provides programmable TTL / LVTTL output clocks and strobes, and supports external clock and strobe. A programmable PLL (phase locked loop) provides configurable clock frequencies and delays. An LVDS output clock is also provided.
The GX5290 Series's sequencer can halt or pause on a defined address or loop through the entire memory as well as loop on a defined address range or through a defined block of memory.